Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM).
DRAMs use one or more arrays of memory cells arranged in rows and columns. Each of the rows of memory cells is activated by a corresponding row line that is selected from a row address. A pair of complementary digit lines are provided for each column of the array and a sense amplifier coupled to the digit lines for each column is enabled responsive to a respective column address. The sense amplifier senses a small voltage differential between the digit lines and amplifies such voltage differential.
The digit lines of each column are typically precharged to one-half the supply voltage VCC prior to being coupled to a memory cell. Coupling the memory cell to the digit line causes the voltage on the digit line to increase slightly above the VCC/2 level or decrease slightly below the VCC/2 level in response to the memory cell status.
The sense amplifier compares this altered voltage to the voltage VCC/2 on the complementary digit line and drives the digit line that is coupled to the memory cell to the full high or low logic level. This restores the voltage on the memory cell to the voltage corresponding to the logic level that is stored in the memory cell. The logic level stored in the memory cell can then be read by determining the differential voltage between the digit lines.
As is well known in the art, DRAM memory cells must be periodically refreshed to avoid loss of data. The memory cells in a row can be refreshed by simply coupling the memory cells in the row to one of the digit lines after enabling the sense amplifiers. The sense amplifiers then restore the voltage level on the memory cell capacitor to a voltage level corresponding to the stored data bit. The permissible time between refresh cycles without losing data depends on various factors such as rate of charge dissipation in the memory capacitor. It is desirable to reduce the number of refresh cycles in a memory device since such a reduction also reduces the number of interruptions required of a system controller to service the refresh.
One way to extend the data retention time while also reducing the required refresh cycles for the memory cells is for a DRAM to operate in a half-density mode. When a DRAM is operated in a half-density mode, two addresses are actually refreshed for every one address that is accessed while reducing the periodicity of the refresh commands.
However, one problem with the half-density mode of operation in a DRAM is that double charge dumping occurs to the sense amplifier during each refresh cycle due to the two memory addresses being accessed. Therefore, the current requirements for the memory device operating in the half-density mode are greater than a memory device having a density comparable to the reduced size of the half-density mode device. Additionally, such an increase in current during these refresh cycles may violate some current specifications for certain memory devices.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to implement half-density mode in a memory device without an increase in power requirements.